UT Austin TIE NGMM Center

Overview

A Packaging Foundry for Stacked Chips

The Texas Institute for Electronics (TIE) at UT Austin is building the Next-Generation Microelectronics Manufacturing (NGMM) Center, a fab for 3D heterogeneous integration (3DHI): stacking chips made on different processes and materials, silicon and non-silicon, into one package. TIE describes it as the only advanced packaging fab in the world dedicated to 3DHI.

DARPA committed $840M in July 2024 and the State of Texas $552M before it, about $1.4B in all. The center runs high-mix, low-volume production for the Department of Defense, universities and companies, the step between a lab prototype and a commercial fab that US microelectronics has lacked. Its consortium includes more than 30 defense and chip companies, among them AMD, Applied Materials, Canon, Intel, Micron, Raytheon and Resonac, plus 18 universities.

1. 1988SEMATECH, the federal and industry chip consortium, opens in the building now called MR2
2. 2007SEMATECH moves its headquarters to Albany, New York
3. 2021TIE founded at UT Austin by S.V. Sreenivasan, Paras Ajay, Larry Dunn and Shrawan Singhal, out of the NSF-funded NASCENT center
4. 2023Texas commits $552M; UT retains the MR2 building for TIE
5. July 2024DARPA awards $840M under the Next-Generation Microelectronics Manufacturing program
6. 2024 to 2027Phase 1: commission both fabs, install and qualify tools, set consortium design and process standards
7. 2027 to 2029Phase 2: build 3DHI hardware prototypes for the Department of Defense and automate production

Facilities

Two Fabs: Production and R&D

The Pilot Fab occupies the Montopolis Research Center building (MR2), SEMATECH's home in the 1990s and 2000s. Reusing its roughly 66,000 sq ft of Class 10 (ISO 4) cleanroom and 28,000 sq ft utility building saved years over a new building; this is where wafer-level 3DHI packaging runs.

The Secure R&D Fab in the Microelectronics and Engineering Research building (MER) develops the process steps, equipment and materials that move into the Pilot Fab. It starts from the NASCENT center's 6,000 sq ft of Class 100 and Class 1000 cleanroom and adds about 18,000 sq ft of cleanroom plus more than 20,000 sq ft of utilities, paid for by the state.

Program

Three Exemplar Devices

Phase 2 proves the process flows on three devices, each a different kind of stack:

In Austin

The Austin Packaging Cluster

Advanced packaging is the step that decides whether chips from different fabs and nodes can be combined into one working system, and it is the step the US has done least of at home. TIE sits beside the rest of Austin's chip work: AMD and Apple's design teams, NXP and Samsung's Austin fabs, Samsung Taylor, and SpaceX, which plans to package radiation-tolerant chips at its Bastrop Complex.

TIE's leadership has changed since the award. John Schreck, formerly a senior vice president at Micron, became CEO in 2022; Dwayne LaBrake, formerly president and CEO of Canon Nanotechnologies, now leads it.

Constraints

Schedule and Workforce

The Phase 2 prototypes are the test. The center has to deliver working 3DHI hardware to the Department of Defense on DARPA's schedule; slips on the three exemplars would weaken its case with commercial customers.

Staffing is the other limit. Packaging process engineers, equipment technicians and materials scientists are scarce, and TIE competes for them with Samsung, NXP and the other Austin fabs. TIE trains technicians with Austin Community College.

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